This application claims priority of Korean Patent Application No. 87415/2001 filed Dec. 28, 2001, under 35 U.S.C. xc2xa7119, which is herein fully incorporated by reference.
1. Field of the Invention
The invention relates to an active matrix liquid crystal display device having an active panel on which a thin film transistor (TFT) and a pixel electrode connected to the TFT are arranged in a matrix. Especially, the invention relates to a high resolution liquid crystal display device having a shorting bar for testing a thin film transistor.
2. Description of the Background Art
Thin film type flat display devices are under intensive development thanks to their ergonomic advantages of being easily used at any location. Especially, liquid crystal display devices have high resolution and reaction speeds sufficiently fast to realize a mobile image.
Liquid crystal display devices are based on the exploitation of optical anisotropy and polarizability of liquid crystals. That is, by artificially controlling an orientation direction of liquid crystal molecules which has a direction by using their dielectric anisotropy, light can be transmitted or blocked by the optical anisotropy according to the orientation direction. This phenomenon is applied for use in a screen display device.
Currently, an active matrix liquid crystal display device, in which a thin film transistor and a pixel electrode connected thereto are arranged in a matrix form, has wide use thanks to its excellent picture quality.
The structure of a conventional liquid crystal display device will now be described.
One panel (or a color filter panel) of the liquid crystal display device has a structure that red, blue and green color filters are sequentially disposed at the position of pixels on a transparent substrate. A black matrix is formed in mesh form between the color filters. A common electrode is formed on the color filter.
The other panel of the liquid crystal display device has a structure such that pixel electrodes are arranged at portions of pixels designed in matrix form on a transparent substrate.
Signal lines are formed in a horizontal direction of the pixel electrodes, and data lines are formed in a vertical direction of the pixel electrodes.
A thin film transistor is formed at a corner of the pixel electrode to drive the pixel electrode. A gate electrode of the thin film transistor is connected to the signal line (thus, it is also called a gate line), and a source electrode of the thin film transistor is connected to the data line (thus, it is also called a source line).
A pad part is formed at an end of each line to connect the line to an external driving circuit.
The two panels are attached facing one another with a specified space therebetween (the space is called a cell gap), in which liquid crystal material is filled.
In fabricating the active panel of the liquid crystal display device, a method of forming the shorting bar for testing the driving state of each element simultaneously in the process of fabricating the elements will now be described.
FIG. 1 shows a conventional plane structure of one part of the active substrate. FIGS. 2A through 2E show conventional sequential section structures in fabricating the active substrate taken along line IIxe2x80x94II of FIG. 1. FIGS. 3A through 3E show conventional sequential section structures in fabricating the active substrate taken along line IIIxe2x80x94III of FIG. 1. FIGS. 4A through 4E show conventional sequential section structures in fabricating the active substrate taken along line IVxe2x80x94IV of FIG. 1.
As shown in FIGS. 1, 2A, 3A and 4A, aluminum or aluminum alloy is deposited on a transparent substrate 1 and patterned to form a gate electrode 11, a gate line 13, a gate pad 15, a source pad 25 and a shorting bar 45.
The gate lines 13 are isolatedly arranged in line, and the gate electrode 11 is formed by being extended from a certain position of the gate line 13. The gate pad 15 is formed at an end of the gate line 13, and the source pad 25 is formed at an end of the source line 23 (to be formed later). The shorting bar 45 is formed at an outer circumference of the substrate 1 and connects the gate pad 15 and the source 25.
In general, a hillock can easily grow on the surface of a metal layer containing aluminum, thereby causing trouble when other materials are afterwards stacked on the metal layer.
Thus, in order to prevent a hillock from forming, the metal layer is anodized to form an anodized film 19. At this time, since the gate electrode 11, the gate line 13, the gate pad 15 and the source pad 25 are connected to each other through the shorting bar 45, it is suitable for anodic oxidation.
In this respect, however, current can scarcely penetrate the anodized surface. Thus, anodic oxidation is preferably not performed on the gate pad 15 to be connected to an external terminal and the source pad 25. For this, a film is formed on the gate pad 15 and the source pad 25 by using a photoresist to prevent anodic oxidation, and then the anodic oxidation process is performed.
As a result, at the thin film transistor part, as shown in FIG. 2A, the gate electrode 11 including the anodized film is formed at the surface of the substrate 1.
Also, at the part where the gate pad 15 and the shorting bar 45 are formed, as shown in FIG. 3A, the shorting bar 45 and the gate line 13 including the anodized film 19 are formed at the surface of the substrate 1, and the gate pad 15 is formed at the surface of the substrate 1, including no anodized film 19.
At the part where the source pad 25 and the shorting bar 45 are formed, as shown in FIG. 4A, the shorting bar 45 including the anodized film 19 is formed at the surface of the substrate 1, and the source pad 25 is formed at the surface of the substrate 1, such that the source pad 25 includes no anodized film 19.
With reference to FIGS. 2B, 3B and 4B, silicon oxide or silicon nitride is deposited at the entire surface of the substrate 1 with the gate electrode 11, the gate line 13, the gate pad 15, the source pad 25 and the shorting bar 45 formed thereon, so as to form a gate insulation film 17.
FIG. 2B shows an intrinsic semiconductor material and a doped semiconductor material containing an impurity are formed in succession on the gate insulation film 17, and then patterned by using photolithography to form a semiconductor layer 35 and an impurity semiconductor layer 37 at that part of the thin film transistor.
And then, as shown in FIGS. 3B and 4B, the gate insulation film 17 at the part covering the gate pad 15 and the source pad 25 is etched to form first gate contact holes 51 and first source contact holes 61.
The first gate contact holes 51 expose the non-anodized portion of the gate pad 15. The first source contact holes 61 expose the non-anodized portion of the source pad 26.
With reference to FIGS. 2C, 3C and 4C, a metal such as chromium is deposited on the entire surface of the substrate with the semiconductor layer 35 and the impurity semiconductor layer 37 formed thereon. Then, patterning forms a source electrode 21, a drain electrode 31, a source line 23, a gate pad intermediate electrode 55 and a source pad intermediate electrode 65.
Accordingly, at the part where the thin film transistor is formed, as shown in FIG. 2C, the source electrode 21 and the drain electrode 31 are patterned to face each other over the gate electrode 11. The impurity semiconductor layer 37 exposed through the source electrode 21 and the drain electrode 31 is etched so that the source electrode 21 and the drain electrode 31 can be electrically isolated.
At the part where the gate pad 15 is formed, as shown in FIG. 3C, the gate pad intermediate electrode 55 is connected to the gate pad 15 through the first gate contact holes 51 formed at the gate insulation film 17.
At the part where the source pad 25 is formed, as shown in FIG. 4C, the source pad intermediate electrode 65 is connected to the source pad 25 through the first source contact holes 61 formed at the gate insulation film 17.
With reference to FIGS. 2D, 3D and 4D, the source electrode 21, a passivation film 41 is formed over the substrate 1 with the source line 23, the drain electrode 31, the gate pad intermediate electrode 55 and the source pad intermediate electrode 65 formed thereon.
Then, at the part where the thin film transistor is formed, as shown in FIG. 2D, a portion of the passivation film 41 is etched by the photolithography to form a drain contact hole 71 exposing a portion of the drain electrode 31.
At the part where the gate pad 15 is formed, as shown in FIG. 3D, a portion of the passivation film 51 is etched by photolithography to form the second gate contact holes 53 exposing a portion of the gate pad intermediate electrode 55.
At the part where the source pad 25 is formed, as shown in FIG. 4D, a portion of the passivation film 41 is etched by photolithography to form the second source contact holes 63 exposing a portion of the source pad intermediate electrode 65.
As the passivation film 41, an inorganic insulation film made of a silicon nitride or silicon oxide material has been conventionally used. Efforts to improve the aperture of a liquid crystal cell includes adopting an organic insulation film such as BCB (benzocyclobutene), SOG (spin on glass), polyacrylics or polymethacrylics as the passivation film.
When forming the conductive films, the cross region (xe2x80x98Axe2x80x99 of FIG. 1) connecting the gate pad 15 and the source pad 25 of the shorting bar 45 (to prevent occurrence of static electricity) no longer needs to be connected, so it is selectively removed by etching using photolithography.
As a result, the shorting bar 45 proceeding in the line direction connects the source pads 25 (thus, it is called the source shorting bar). Meanwhile, the shorting bar 45 proceeding in the column direction connects the gad pads 15 (thus, it is called the gate shorting bar).
With reference to FIGS. 2E, 3E and 4E, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) is deposited at the entire surface of the passivation film 41 and patterned by photolithography.
Accordingly, at the part where the thin film transistor is formed, as shown in FIG. 2, the pixel electrode 33 is connected to the drain electrode 31 through the drain contact hole 71.
At the part where the gate pad 15 is formed, as shown in FIG. 3E, a gate pad connection terminal 57 connects to a gate pad intermediate electrode 55 through the second gate contact holes 53.
At the part where the source pad 25 is formed, as shown in FIG. 4E, a source pad connection terminal 67 connects to a source pad intermediate electrode 65 through the second source contact holes 63.
In the conventional active substrate as described above, when the gate line is patterned in order to facilitate the anodic oxidation, the shorting bar for testing the thin film transistor is formed being electrically connected to every gate pad and source pad.
Then, in order for the shorting bar to be connected to the gate pads and the source pads, the cross region of the shorting bar is selectively removed, thereby separating the shorting bar to form a separate gate shorting bar connecting the gate pads and a separate source shorting bar connecting source pads.
The process of testing of the active panel having shorting bar for testing the thin film transistor will now be described.
First, when a gate turn-on voltage is applied to the gate shorting bar, the gate turn-on voltage is applied to the gate of each thin film transistor through every gate pad and every gate line, so that each thin film transistor is turned on.
Next, when a test voltage is applied to the source shorting bar, the test voltage is applied to each source electrode of the thin film transistor through every source pad and every source line of the active panel.
Since the thin film transistor is turned on, the test voltage applied to the source electrode of the thin film transistor is applied to the drain electrode via the conductive channel.
The drain electrode is connected to the pixel electrode, so that the test voltage is resultantly applied to every pixel electrode of the active panel.
Therefore, by scanning whether or not a voltage is applied to the pixel electrode, a open defect of the gate lines or the source lines can be tested.
However, the conventional art has the following shortcomings.
First, if a short occurs between the neighboring gate lines or neighboring source lines, the open defect can not be detected properly.
Second, since the anodic oxidation process and the mask process for removing the cross region of the shorting bar are additionally required, it takes a long time to manufacture a product and product manufacturing cost increases. In addition, an increase in defect occurrence due to mask misalignment degrades the yield.
Therefore, to solve those shortcomings, a low resolution liquid crystal display device having a shorting bar for testing a thin film transistor and capable of detecting short defects of gate lines and source lines and a driving defect of a thin film transistor (when a short occurs between neighboring gate lines or neighboring source lines) while reducing the number of mask processes, have been proposed by the same applicant of the invention (Korean Patent No. 10-0244449 and Korean Patent No. 10-0271038).
The disclosure of Korean Patent No. 10-0244449 and Korean Patent No. 10-0271038 can be described as follows: When gate lines are formed, rather than taking anodic oxidation method to prevent a hillock generating at the surface of aluminum, aluminum is protected with a metal having excellent surface stability (such as chromium), thereby reducing the number of masking processes used in the step of anodic oxidation and in the step of forming the contact hole at the pad part. In addition, the shorting bar for detecting a defect in the gate lines and the source lines is separately formed to odd number lines and even number lines, thereby testing a short defect in each line as well as testing a short defect of two neighboring lines.
That is, with reference to FIG. 5, gate lines 113 are isolatedly arranged in lines on a substrate 101, and source lines 123 are isolatedly arranged in columns. Thus, the gate lines 113 and the source lines 123 intersect each other.
At this time, a unit liquid crystal cell is defined at every intersect portion of the gate lines 113 and the source lines 123, and the unit liquid crystal cell includes a thin film transistor TFT and a pixel electrode 133 connected to a drain electrode (not shown) of the thin film transistor TFT.
Gate pads 115 are formed at each of one ends of the gate lines 113 and connected to the gate lines 113, and first and second gate shorting bars 145 and 146 are formed connected to the gate pads 115. The first gate shorting bar 145 is connected to odd number gate pads 115, while the second gate shorting bar 146 is connected to the even number gate pads 115.
Source pads 125 are formed at each of one ends of the source lines 123 and connected to the source lines 123, and first and second source shorting bars 155 and 156 are formed connected to the source pads 125. The first source shorting bar 155 is connected to the odd number source pads 125 and the second source shorting bar 156 is connected to the even number source pads 125.
The process for testing the active panel having the shorting bar for testing a thin film transistor will now be described.
First, when a turn-on voltage is applied to the first gate shorting bar 145 or to the second gate shorting bar 146, the gate turn-on voltage is applied to the gate of the thin film transistor TFT through the odd number or even number gate pads 115 and the gate lines 113 of the active panel, so that the thin film transistor TFT turns on.
When a test voltage is applied to the first and second source shorting lines, the test voltage is applied to the source electrode of the thin film transistor TFT through the odd number and even number source pads 125 and the source lines 123 of the active panel.
The test voltage applied to the source electrode of the thin film transistor TFT is applied to the drain electrode via the conductive channel of the turned-on thin film transistor TFT. Since the drain electrode is connected to the pixel electrode 133, the test voltage is resultantly applied to the pixel electrode 133 connected to the drain electrode of the turned-on thin film transistor TFT of the active panel.
The test voltage is differently applied to the first and second source shorting bars 155 and 156. That is, for example, 10 V test voltage is applied to the first source shorting bar 155 and 5V test voltage is applied to the second source shorting bar 156.
Since the odd number source pads 125 are connected to the first source shorting bar 155 and the even number source pads 125 are connected to the second source shorting bar 156, the pixel electrodes 133, to which the 10 V test voltage has been applied through the odd number source pads 125 and the source lines 123 connected thereto, are compared to test for a short defect, and the pixel electrodes 133, to which the 5V test voltage has been applied through the even number source pads 125 connected to the second source shorting bar 156 and source lines 123 connected thereto, are compared to test for a short defect.
Therefore, even if a open defect occurs between neighboring source lines 123, the short defect of each source line 123 can be effectively tested, and the open defect of neighboring source lines 123 can be tested.
As described above, the conventional low-resolution liquid crystal display device has shorting bars for testing a thin film transistor in which first and second gate shorting bars are respectively connected to odd number gate pads and even number gate pads, and first and second source shorting bars are respectively connected to odd number source pads and even number source pads. The active channel can be effectively tested in a low-resolution product which is comparatively spacious in terms of isolation distance between pixel electrodes and the area of the pixel electrode. But when it comes to a high resolution product in which the isolation distance between pixel electrodes and the area of the pixel electrode are relatively short and narrow compared to those of the low resolution product, it is not possible to test the active panel.
The invention, in part, provides a liquid crystal display device having a shorting bar for testing a thin film transistor that is capable of testing an active panel of a high resolution product.
The invention, in part, pertains to a liquid crystal display device having thin film transistors, which contains gate lines and source lines arranged to intersect each other on a substrate, gate pads connected to the gate lines at one ends of the gate lines and source pads connected to the source lines at one ends of the source lines, and first and second source shorting bars at least two-by-two alternately connected to the source pads. The first and second shorting bars can also be three-by-three alternately connected.
The invention, in part, pertains to a liquid crystal display device having gate lines and source lines arranged to intersect each other on a substrate, a unit liquid crystal cell defined at every intersection region of the gate lines and the source lines, a thin film transistor provided in the unit liquid crystal cell and a pixel electrode connected to a drain electrode of the thin film transistor, gate pads connected to the gate lines at one ends of the gate lines and source pads connected to the source pads at one ends of the source lines, first and second gate shorting bars selectively connected to the gate pads, and first and second source shorting bars two-by-two alternately connected to the source pads. The first and second shorting bars can also be three-by-three alternately connected.
The invention, in part, pertains to a method for testing a liquid crystal display device, which includes providing the liquid crystal display device having thin film transistors, the liquid crystal display device comprising gate lines and source lines arranged to intersect each other on a substrate, gate pads connected to the gate lines at one ends of the gate lines and source pads connected to the source lines at one ends of the source lines, and first and second source shorting bars at least two-by-two alternately connected to the source pads. Different high and low test voltages are applied to the first and second source shorting bars, and the method scans, as one, adjacent pixel electrodes to which the same test voltage has been applied, then comparing tests for defects. The high voltage can be 10 volts. The low voltage can be 5 volts.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.